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M29W640FT M29W640FB
64 Mbit (8Mb x8 or 4Mb x16, Page, Boot Block) 3V Supply Flash Memory
Features summary
Supply Voltage - VCC = 2.7V to 3.6V for Program, Erase, Read - VPP =12 V for Fast Program (optional) Asynchronous Random/Page Read - Page Width: 4 Words - Page Access: 25ns - Random Access: 60ns, 70ns Programming Time - 10 s per Byte/Word typical - 4 Words/8 Bytes Program 135 memory blocks - 1 Boot Block and 7 Parameter Blocks, 8 KBytes each (Top or Bottom Location) - 127 Main Blocks, 64 KBytes each Program/Erase Controller - Embedded Byte/Word Program algorithms Program/Erase Suspend and Resume - Read from any Block during Program Suspend - Read and Program another Block during Erase Suspend Unlock Bypass Program command - Faster Production/Batch Programming VPP/WP pin for Fast Program and Write Protect Temporary Block Unprotection mode Common Flash Interface - 64-bit Security Code Extended Memory Block - Extra block used as security block or to store additional information Low power consumption - Standby and Automatic Standby 100,000 Program/Erase cycles per block Figure 1. Packages
TSOP48 (N) 12 x 20mm
FBGA
TFBGA48 (ZA) 6x8mm
Electronic Signature - Manufacturer Code: 0020h Table 1. Device Codes
Device Code 22EDh 22FDh
Root Part Number M29W640FT M29W640FB
ECOPACK(R) packages
December 2005
Rev3 1/72
www.st.com 1
M29W640FT, M29W640FB
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Input/Output or Address Input (DQ15A-1) . . . . . . . . . . . . . . . . . . . . . . 11 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VPP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VCC Supply Voltage (2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 3.2 3.3 3.4 3.5 3.6 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.1 3.6.2 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1.1 4.1.2 4.1.3 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.10 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2
Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3
Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3.1 4.3.2 4.3.3 Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . . . . . 27
5
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1 5.2 5.3 5.4 5.5 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 7 8 9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
C.1 C.2 Factory Locked Extended Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Appendix D Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
D.1 D.2 Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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M29W640FT, M29W640FB
List of tables
Table 1. Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Program, Erase Times and Program, Erase Endurance Cycles. . . . . . . . . . . . . . . . . . . . . 29 Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data. . . 44 TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data. . . . . . 45 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Top Boot Block Addresses, M29W640FT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Bottom Boot Block Addresses, M29W640FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Programmer Technique Bus Operations, BYTE = VIH or VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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List of figures
Figure 1. Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Page Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . . 44 TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, Package Outline . . . . . . . . . . . . . 45 Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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1 Summary description
1
Summary description
The M29W640F is a 64 Mbit (8Mb x8 or 4Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected in units of 256 KByte (generally groups of four 64 KByte blocks), to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The device features an asymmetrical blocked architecture. The device has an array of 135 blocks: 8 Parameters Blocks of 8 KBytes each (or 4 KWords each) 127 Main Blocks of 64 KBytes each (or 32 KWords each) M29W640FT has the Parameter Blocks at the top of the memory address space while the M29W640FB locates the Parameter Blocks starting from the bottom. The M29W640F has an extra block, the Extended Block, of 128 Words in x16 mode or of 256 Byte in x8 mode that can be accessed using a dedicated command. The Extended Block can be protected and so is useful for storing security information. However the protection is not reversible, once protected the protection cannot be undone. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The VPP/WP signal is used to enable faster programming of the device, enabling multiple word/ byte programming. If this signal is held at VSS, the boot block, and its adjacent parameter block, are protected from program and erase operations. The device supports Asynchronous Random Read and Page Read from all blocks of the memory array. The memories are offered in TSOP48 (12x 20mm) and TFBGA48 (6x8mm, 0.8mm pitch) packages. In order to meet environmental requirements, ST offers the M29W640FT and the M29W640FB in ECOPACK(R) packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. The memory is delivered with all the bits erased (set to 1).
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1 Summary description
M29W640FT, M29W640FB
Logic Diagram
VCC VPP/WP
Figure 1.
22 A0-A21 W E G RP M29W640FT M29W640FB
15 DQ0-DQ14 DQ15A-1 BYTE RB
VSS
AI11250
Table 1.
A0-A21 DQ0-DQ7 DQ8-DQ14
Signal Names
Address Inputs Data Inputs/Outputs Data Inputs/Outputs Data Input/Output or Address Input (or Data Input/Output) Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Byte/Word Organization Select Supply Voltage Supply Voltage for Fast Program (optional) or Write Protect Ground Not Connected Internally
DQ15A-1 (or DQ15) E G W RP RB BYTE VCC VPP/WP VSS NC
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Figure 2. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP A21 VPP/WP RB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
AI11251
1 Summary description
M29W640FT M29W640FB 12 13 37 36
24
25
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1 Summary description
M29W640FT, M29W640FB
Figure 3.
TFBGA48 Connections (Top view through package)
1 2 3 4 5 6
A
A3
A7
RB
W
A9
A13
B
A4
A17
VPP/WP
RP
A8
A12
C
A2
A6
A18
A21
A10
A14
D
A1
A5
A20
A19
A11
A15
E
A0
DQ0
DQ2
DQ5
DQ7
A16
F
E
DQ8
DQ10
DQ12
DQ14
BYTE
G
G
DQ9
DQ11
VCC
DQ13
DQ15 A-1
H
VSS
DQ1
DQ3
DQ4
DQ6
VSS
AI11554
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2 Signal descriptions
2
Signal descriptions
See Figure 1: Logic Diagram, and Table 1: Signal Names, for a brief overview of the signals connected to this device.
2.1
Address Inputs (A0-A21)
The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller.
2.2
Data Inputs/Outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller.
2.3
Data Inputs/Outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.
2.4
Data Input/Output or Address Input (DQ15A-1)
When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A-1 Low will select the LSB of the addressed Word, DQ15A-1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise.
2.5
Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored.
2.6
Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
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2.7
Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory's Command Interface.
2.8
VPP/Write Protect (VPP/WP)
The VPP/Write Protect pin provides two functions. The VPP function allows the memory to use an external high voltage power supply to reduce the time required for Unlock Bypass Program operations. The Write Protect function provides a hardware method of protecting the two outermost boot blocks. The VPP/Write Protect pin must not be left floating or unconnected. When VPP/Write Protect is Low, VIL, the memory protects the two outermost boot blocks; Program and Erase operations in this block are ignored while VPP/Write Protect is Low, even when RP is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the two outermost boot blocks. Program and Erase operations can now modify the data in the two outermost boot blocks unless the block is protected using Block Protection. Applying VPPH to the VPP/WP pin will temporarily unprotect any block previously protected (including the two outermost parameter blocks) using a High Voltage Block Protection technique (In-System or Programmer technique). See Table 2: Hardware Protection for details. When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than tVHVPP, see Figure 13: Accelerated Program Timing Waveforms. Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. A 0.1F capacitor should be connected between the VPP/Write Protect pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, IPP. Table 2. Hardware Protection
RP VIH VIL VID VIH or VID VPPH VID VIH or VID Function 2 outermost parameter blocks protected from Program/Erase operations All blocks temporarily unprotected except the 2 outermost blocks All blocks temporarily unprotected All blocks temporarily unprotected
VPP/WP
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2 Signal descriptions
2.9
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if VPP/WP is at VIL, then the two outermost boot blocks will remain protected even if RP is at VID. A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 16: Reset/Block Temporary Unprotect AC Characteristics and Figure 12: Reset/Block Temporary Unprotect AC Waveforms, for more details. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH.
2.10
Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 16: Reset/Block Temporary Unprotect AC Characteristics and Figure 12: Reset/Block Temporary Unprotect AC Waveforms, for more details. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.
2.11
Byte/Word Organization Select (BYTE)
The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in x8 mode, when it is High, VIH, the memory is in x16 mode.
2.12
VCC Supply Voltage (2.7V to 3.6V)
VCC provides the power supply for all operations (Read, Program and Erase). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1F capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Program and Erase operations, ICC3.
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2.13
VSS Ground
VSS is the reference for all voltage measurements. The device features two VSS pins which must be both connected to the system ground.
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3 Bus operations
3
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Table 3: Bus Operations, BYTE = VIL and Table 4: Bus Operations, BYTE = VIH, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.
3.1
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 8: Read Mode AC Waveforms, and Table 13: Read AC Characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write to the Command Interface. To speed up the read operation the memory array can be read in Page mode where data is internally read and stored in a page buffer. The Page has a size of 4 Words and is addressed by the address inputs A0-A1. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figure 10: Write AC Waveforms, Write Enable Controlled, Figure 11: Write AC Waveforms, Chip Enable Controlled, and Table 14: Write AC Characteristics, Write Enable Controlled and Table 15: Write AC Characteristics, Chip Enable Controlled, for details of the timing requirements.
3.3
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4
Standby
When Chip Enable is High, VIH , the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC 0.2V. For the Standby current level see Table 12: DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes.
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3.5
Automatic Standby
If CMOS levels (VCC 0.2V) are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.
3.6
Special Bus Operations
Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins.
3.6.1
Electronic Signature
The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 3: Bus Operations, BYTE = VIL and Table 4: Bus Operations, BYTE = VIH.
3.6.2
Block Protect and Chip Unprotect
Groups of blocks can be protected against accidental Program or Erase. The Protection Groups are shown in Appendix A: Block addresses Table 20 and Table 21. The whole chip can be unprotected to allow the data inside the blocks to be changed. The VPP /Write Protect pin can be used to protect the two outermost boot blocks. When VPP / Write Protect is at VIL the two outermost boot blocks are protected and remain protected regardless of the Block Protection Status or the Reset/Block Temporary Unprotect pin status. Block Protect and Chip Unprotect operations are described in Appendix D: Block Protection.
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Table 3. Bus Operations, BYTE = VIL
E VIL VIL X VIH VIL G VIL VIH VIH X VIL W VIH VIL VIH X VIH Address Inputs DQ15A-1, A0-A21 Cell Address Command Address X X A0-A3 = VIL, A6 = VIL, A9 = VID, Others VIL or VIH A0 = VIH, A1-A3= VIL, A6 = VIL, A9 = VID, Others VIL or VIH A0 -A1 = VIH, A2-A3= VIL, A6 = VIL, A9 = VID, Others VIL or VIH A0,A2,A3, A6= VIL, A1= VIH, A9 = VID, A12-A21 = Block Address, Others VIL or VIH
3 Bus operations
Data Inputs/Outputs DQ14-DQ8 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ7-DQ0 Data Output Data Input Hi-Z Hi-Z 20h
Operation Bus Read Bus Write Output Disable Standby Read Manufacturer Code
Read Device Code
VIL
VIL
VIH
Hi-Z
EDh (M29W640FT) FDh (M29W640FB) 80h (factory locked) 00h (Customer Lockable)
Read Extended Memory Block Verify Code
VIL
VIL
VIH
Hi-Z
Read Block Protection Status
VIL
VIL
VIH
Hi-Z
01h (protected) 00h (unprotected)
1. X = VIL or VIH.
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Table 4.
Bus Operations, BYTE = VIH
E VIL VIL X VIH VIL VIL G VIL VIH VIH X VIL VIL W VIH VIL VIH X VIH VIH Address Inputs A0-A21 Cell Address Command Address X X A0-A3 = VIL, A6 = VIL, A9 = VID, Others VIL or VIH A0 = VIH, A1-A3= VIL, A6 = VIL, A9 = VID, Others VIL or VIH A0 -A1 = VIH, A2-A3= VIL, A6 = VIL, A9 = VID, Others VIL or VIH A0,A2,A3, A6= VIL, A1 = VIH, A9 = VID, A12-A21 = Block Address, Others VIL or VIH Data Inputs/Outputs DQ15A-1, DQ14-DQ0 Data Output Data Input Hi-Z Hi-Z 0020h 22EDh (M29W640FT) 22FDh (M29W640FB) 80h (factory locked) 00h (Customer Lockable)
Operation Bus Read Bus Write Output Disable Standby Read Manufacturer Code Read Device Code Read Extended Memory Block Verify Code
VIL
VIL
VIH
Read Block Protection Status
VIL
VIL
VIH
0001h (protected) 0000h (unprotected)
1. X = VIL or VIH.
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4 Command Interface
4
Command Interface
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16-bit or 8-bit mode. See either Table 5, or Table 6, depending on the configuration that is being used, for a summary of the commands.
4.1
4.1.1
Standard commands
Read/Reset command
The Read/Reset command returns the memory to its Read mode. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/ Reset command. The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. If the Read/Reset command is issued during the timeout of a Block Erase operation then the memory will take up to 10s to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend.
4.1.2
Auto Select command
The Auto Select command is used to read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Memory Block Verify Code. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset commands are accepted in Auto Select mode, all other commands are ignored. In Auto Select mode, the Manufacturer Code and the Device Code can be read by using a Bus Read operation with addresses and control signals set as shown in Table 3: Bus Operations, BYTE = VIL and Table 4: Bus Operations, BYTE = VIH, except for A9 that is `Don't Care'. The Block Protection Status of each block can be read using a Bus Read operation with addresses and control signals set as shown in Table 3: Bus Operations, BYTE = VIL and Table 4: Bus Operations, BYTE = VIH, except for A9 that is `Don't Care'. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output (in 8-bit mode). The protection status of the Extended Memory block, or Extended Memory Block Verify code, can be read using a Bus Read operation with addresses and control signals set as shown in Table 3: Bus Operations, BYTE = VIL and Table 4: Bus Operations, BYTE = VIH, except for A9 that is `Don't Care'. If the Extended Block is "Factory Locked" then 80h is output on Data Input/ Outputs DQ0-DQ7, otherwise 00h is output (8-bit mode).
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4.1.3
Read CFI Query command
The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the device is in the Read Array mode, or when the device is in Autoselected mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/Reset command would be needed if the device is to be put in the Read Array mode from Autoselected mode. See Appendix B: Common Flash Interface (CFI), Tables 22, 23, 24, 25, 26 and 27 for details on the information contained in the Common Flash Interface (CFI) memory area.
4.1.4
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 7: Program, Erase Times and Program, Erase Endurance Cycles. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to '1'. All previous data is lost.
4.1.5
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50s after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50s of the last block. The 50s timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register section for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored.
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4 Command Interface
During the Block Erase operation the memory will ignore all commands except the Erase Suspend command. Typical block erase times are given in Table 7: Program, Erase Times and Program, Erase Endurance Cycles. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to '1'. All previous data in the selected blocks is lost.
4.1.6
Erase Suspend command
The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within the Erase Suspend Latency time of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted.
4.1.7
Erase Resume command
The Erase Resume command must be used to restart the Program/Erase Controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An erase can be suspended and resumed more than once.
4.1.8
Program Suspend command
The Program Suspend command allows the system to interrupt a program operation so that data can be read from any block. When the Program Suspend command is issued during a program operation, the device suspends the program operation within the Program Suspend Latency time (see Table 7: Program, Erase Times and Program, Erase Endurance Cycles for value) and updates the Status Register bits. After the program operation has been suspended, the system can read array data from any address. However, data read from Program-Suspended addresses is not valid. The Program Suspend command may also be issued during a program operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend
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or Program Suspend. If a read is needed from the Extended Block area (One-time Program area), the user must use the proper command sequences to enter and exit this region. The system may also issue the Auto Select command sequence when the device is in the Program Suspend mode. The system can read as many Auto Select codes as required. When the device exits the Auto Select mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Auto Select command sequence for more information.
4.1.9
Program Resume command
After the Program Resume command is issued, the device reverts to programming. The controller can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command, to exit the Program Suspend mode and to continue the programming operation. Further issuing of the Resume command is ignored. Another Program Suspend command can be written after the device has resumed programming.
4.1.10 Program command
The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase Controller. Programming can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 4.1.8: Program Suspend command and Section 4.1.9: Program Resume command). If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 7: Program, Erase Times and Program, Erase Endurance Cycles. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'.
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4.2
Fast Program commands
There are four Fast Program commands available to improve the programming throughput, by writing several adjacent words or bytes in parallel. The Double, Quadruple and Octuple Byte Program commands are available for x8 operations, while the Double Quadruple Word Program command are available for x16 operations. Fast Program commands can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 4.1.8: Program Suspend command and Section 4.1.9: Program Resume command). When VPPH is applied to the VPP/Write Protect pin the memory automatically enters the Fast Program mode. The user can then choose to issue any of the Fast Program commands. Care must be taken because applying a VPPH to the VPP/WP pin will temporarily unprotect any protected block.
4.2.1
Double Byte Program command
The Double Byte Program command is used to write a page of two adjacent Bytes in parallel. The two bytes must differ only in DQ15A-1. Three bus write cycles are necessary to issue the Double Byte Program command. 1. 2. 3. The first bus cycle sets up the Double Byte Program Command. The second bus cycle latches the Address and the Data of the first byte to be written. The third bus cycle latches the Address and the Data of the second byte to be written.
4.2.2
Quadruple Byte Program command
The Quadruple Byte Program command is used to write a page of four adjacent Bytes in parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles are necessary to issue the Quadruple Byte Program command. 1. The first bus cycle sets up the Quadruple Byte Program Command. 2. 3. 4. 5. The second bus cycle latches the Address and the Data of the first byte to be written. The third bus cycle latches the Address and the Data of the second byte to be written. The fourth bus cycle latches the Address and the Data of the third byte to be written. The fifth bus cycle latches the Address and the Data of the fourth byte to be written and starts the Program/Erase Controller.
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4.2.3
Octuple Byte Program command
This is used to write eight adjacent Bytes, in x8 mode, simultaneously. The addresses of the eight Bytes must differ only in A1, A0 and DQ15A-1. Nine bus write cycles are necessary to issue the command: 1. 2. 3. 4. 5. 6. 7. 8. 9. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first Byte to be written. The third bus cycle latches the Address and the Data of the second Byte to be written. The fourth bus cycle latches the Address and the Data of the third Byte to be written. The fifth bus cycle latches the Address and the Data of the fourth Byte to be written. The sixth bus cycle latches the Address and the Data of the fifth Byte to be written. The seventh bus cycle latches the Address and the Data of the sixth Byte to be written. The eighth bus cycle latches the Address and the Data of the seventh Byte to be written. The ninth bus cycle latches the Address and the Data of the eighth Byte to be written and starts the Program/Erase Controller.
4.2.4
Double Word Program command
The Double Word Program command is used to write a page of two adjacent Words in parallel. The two Words must differ only for the address A0. Three bus write cycles are necessary to issue the Double Word Program command. The first bus cycle sets up the Quadruple Word Program Command. The second bus cycle latches the Address and the Data of the first Word to be written. The third bus cycle latches the Address and the Data of the second Word to be written and starts the Program/Erase Controller. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Fast Program commands cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Typical Program times are given in Table 7: Program, Erase Times and Program, Erase Endurance Cycles.
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4.2.5
Quadruple Word Program command
This is used to write a page of four adjacent Words (or 8 adjacent Bytes), in x16 mode, simultaneously. The addresses of the four Words must differ only in A1 and A0. Five bus write cycles are necessary to issue the command: The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first Word to be written. The third bus cycle latches the Address and the Data of the second Word to be written. The fourth bus cycle latches the Address and the Data of the third Word to be written. The fifth bus cycle latches the Address and the Data of the fourth Word to be written and starts the Program/Erase Controller.
4.2.6
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. When VPP is applied to the VPP/Write Protect pin the memory automatically enters the Unlock Bypass mode and the Unlock Bypass Program command can be issued immediately.
4.2.7
Unlock Bypass Program command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. The memory offers accelerated program operations through the VPP/Write Protect pin. When the system asserts VPP on the VPP/Write Protect pin, the memory automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The memory uses the higher voltage on the VPP/Write Protect pin, to accelerate the Unlock Bypass Program operation. Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state.
4.2.8
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass Mode.
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4.3
4.3.1
Block Protection commands
Enter Extended Block command
The device has an extra 256 Byte block (Extended Block) that can only be accessed using the Enter Extended Block command. Three Bus write cycles are required to issue the Extended Block command. Once the command has been issued the device enters Extended Block mode where all Bus Read or Write operations to the Boot Block addresses access the Extended Block. The Extended Block (with the same address as the Boot Blocks) cannot be erased, and can be treated as one-time programmable (OTP) memory. In Extended Block mode the Boot Blocks are not accessible. To exit from the Extended Block mode the Exit Extended Block command must be issued. The Extended Block can be protected, however once protected the protection cannot be undone.
4.3.2
Exit Extended Block command
The Exit Extended Block command is used to exit from the Extended Block mode and return the device to Read mode. Four Bus Write operations are required to issue the command.
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4.3.3
Block Protect and Chip Unprotect commands
Groups of blocks can be protected against accidental Program or Erase. The Protection Groups are shown in Appendix A: Block addresses, Table 20: Top Boot Block Addresses, M29W640FT and Table 21: Bottom Boot Block Addresses, M29W640FB. The whole chip can be unprotected to allow the data inside the blocks to be changed. Block Protect and Chip Unprotect operations are described in Appendix D: Block Protection.
Table 5.
Commands, 16-bit mode, BYTE = VIH
Bus Write Operations Length
Command
1st
2nd
3rd Addr
4th
5th
6th
Addr Data Addr Data 1 Read/Reset 3 Auto Select Program Double Word Program Quadruple Word Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase Block Erase Program/Erase Suspend Program/Erase Resume Read CFI Query Enter Extended Block Exit Extended Block 3 4 3 5 3 2 2 6 6+ 1 1 1 3 4 555 555 555 555 555 555 X X 555 555 X X 55 555 555 AA AA AA 50 56 AA A0 90 AA AA B0 30 98 AA AA 2AA 2AA 55 55 2AA 2AA 2AA PA0 PA0 2AA PA X 2AA 2AA 55 55 55 PD0 PD0 55 PD 00 55 55 X F0
Data Addr Data Addr Data Addr Data
X 555 555 PA1 PA1 555
F0 90 A0 PD1 PD1 20 PA2 PD2 PA3 PD3 PA PD
555 555
80 80
555 555
AA AA
2AA 2AA
55 55
555 BA
10 30
555 555
88 90 X 00
1. X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A-1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don't Care. DQ15A-1 is A-1 when BYTE is VIL or DQ15 when BYTE is VIH.
27/72
4 Command Interface
M29W640FT, M29W640FB
Table 6.
Commands, 8-bit mode, BYTE = VIL
Bus Write Operations Length
Command
1st Add Data F0 AA AA AA 50 56 8B AA
2nd Add Data
3rd Add Data
4th Add Data
5th Add Data
6th Add Data
7th Add Data
8th Add Data Add
9th Data
1 Read/Reset 3 Auto Select Program Double Byte Program Quadruple Byte Program Octuple Byte Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase Block Erase Program/ Erase Suspend Program/ Erase Resume Read CFI Query Enter Extended Block Exit Extended Block 3 4 3 5 9 3
X AAA AAA AAA AAA AAA AAA AAA
555 555 555 PA0 PA0 PA0 555
55 55 55 PD0 PD0 PD0 55
X AAA AAA PA1 PA1 PA1 AAA
F0 90 A0 PD1 PD1 PD1 20 PA PA2 PA2 PA2 PD PD2 PD2 PD2 PA3 PA3 PD3 PD3 PA4 PD4 PA5 PD5 PA6 PD6 PA7 PD7
2
X
A0
PA
PD
2 6 6 + 1
X AAA AAA
90 AA AA
X 555 555
00 55 55 AAA AAA 80 80 AAA AAA AA AA 555 555 55 55 AAA BA 10 30
X
B0
1
X
30
1
AA
98
3
AAA
AA
555
55
AAA
88
4
AAA
AA
555
55
AAA
90
X
00
1. X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A-1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don't Care. DQ15A-1 is A-1 when BYTE is VIL or DQ15 when BYTE is VIH.
28/72
M29W640FT, M29W640FB
Table 7. Program, Erase Times and Program, Erase Endurance Cycles
Parameter Chip Erase Block Erase (64 KBytes) Erase Suspend Latency Time Program (Byte or Word) Double Byte Double Word /Quadruple Byte Program Quadruple Word / Octuple Byte Program Chip Program (Byte by Byte) Chip Program (Word by Word) Chip Program (Double Word/Quadruple Byte Program) Chip Program (Quadruple Word/Octuple Byte Program) Program Suspend Latency Time Program/Erase Cycles (per Block) Data Retention
1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested.
4 Command Interface
Min
Typ(1) (2) 80 0.8
Max(2) 400(3) 6(4) 50(4)
Unit s s s s s s s s s s s s cycles years
10 10 10 10 80 40 20 10
200(3) 200(3) 200(3) 200(3) 400(3) 200(3) 100(3) 50(3) 4
100,000 20
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. 4. Maximum value measured at worst case conditions for both temperature and VCC.
29/72
5 Status Register
M29W640FT, M29W640FB
5
Status Register
Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 8: Status Register Bits.
5.1
Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs '0', the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a '1' during a Bus Read operation within a block being erased. The Data Polling Bit will change from a '0' to a '1' when the Program/ Erase Controller has suspended the Erase operation. Figure 4: Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased.
5.2
Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. Figure 5: Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.
30/72
M29W640FT, M29W640FB
5 Status Register
5.3
Error Bit (DQ5)
The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to '1' when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to '0' back to '1' and attempting to do so will set DQ5 to `1'. A Bus Read operation to that address will show the bit is still `0'. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'.
5.4
Erase Timer Bit (DQ3)
The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to '1'. Before the Program/Erase Controller starts the Erase Timer Bit is set to '0' and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read.
5.5
Alternative Toggle Bit (DQ2)
The Alternative Toggle Bit can be used to monitor the Program/Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly.
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5 Status Register
M29W640FT, M29W640FB
Table 8.
Status Register Bits
Address Any Address Any Address Any Address Any Address Erasing Block Non-Erasing Block Erasing Block DQ7 DQ7 DQ7 DQ7 0 0 0 0 0 1 DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle No Toggle DQ5 0 0 1 0 0 0 0 0 0 DQ3 - - - 1 0 0 1 1 - DQ2 - - - Toggle Toggle No Toggle Toggle No Toggle Toggle RB 0 0 Hi-Z Hi-Z 0 0 Hi-Z 0 Hi-Z Hi-Z No Toggle Toggle 0 0
Operation Program Program During Erase Suspend Program Error Chip Erase Block Erase before timeout Block Erase
Non-Erasing Block Erasing Block Erase Suspend Non-Erasing Block Good Block Address Erase Error Faulty Block Address
1. Unspecified data bits should be ignored.
Data read as normal 0 0 Toggle Toggle 1 1 1 1
Figure 4.
Data Polling Flowchart
START
READ DQ5 & DQ7 at VALID ADDRESS
DQ7 = DATA NO
YES
NO
DQ5 =1 YES
READ DQ7 at VALID ADDRESS
DQ7 = DATA NO FAIL
YES
PASS
AI90194
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M29W640FT, M29W640FB
Figure 5. Data Toggle Flowchart
START READ DQ6
5 Status Register
READ DQ5 & DQ6
DQ6 = TOGGLE YES
NO
NO
DQ5 =1 YES READ DQ6 TWICE
DQ6 = TOGGLE YES FAIL
NO
PASS
AI90195B
33/72
6 Maximum rating
M29W640FT, M29W640FB
6
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 9.
Symbol TBIAS TSTG VIO VCC VID VPP(3)
Absolute Maximum Ratings
Parameter Temperature Under Bias Storage Temperature Input or Output Voltage(1)(2) Supply Voltage Identification Voltage Program Voltage Min -50 -65 -0.6 -0.6 -0.6 -0.6 Max 125 150 VCC +0.6 4 13.5 13.5 Unit C C V V V V
1. Minimum voltage may undershoot to -2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions. 3. VPP must not remain at 12V for more than a total of 80hrs.
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M29W640FT, M29W640FB
7 DC and AC parameters
7
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 10.
Operating and AC Measurement Conditions
M29W640FT, M29W640FB Parameter Min Max 3.6 85 30 10 0 to VCC VCC/2 V C pF ns V V Unit
VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
2.7 -40
Figure 6.
AC Measurement I/O Waveform
VCC VCC/2 0V
AI05557
Figure 7.
AC Measurement Load Circuit
VPP VCC VCC
25k DEVICE UNDER TEST 25k
CL 0.1F 0.1F
CL includes JIG capacitance
AI05558
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7 DC and AC parameters
M29W640FT, M29W640FB
Table 11.
Symbol CIN COUT
Device Capacitance
Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
1. Sampled only, not 100% tested.
Table 12.
Symbol ILI ILO ICC1 ICC2
DC Characteristics
Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, G = VIH, f = 6MHz E = VCC 0.2V, RP = VCC 0.2V Program/Erase Controller active VPP/WP = VIL or VIH VPP/WP = VPP Min Max 1 1 10 Unit
A A
mA
Supply Current (Standby)
100
A
ICC3
Supply Current (Program/ Erase) Input Low Voltage Input High Voltage Voltage for VPP/WP Program Acceleration Current for VPP/WP Program Acceleration Output Low Voltage Output High Voltage Identification Voltage Program/Erase Lockout Supply Voltage
20 20 -0.5 0.7VCC 0.8 VCC +0.3 12.5 15 0.45 VCC -0.4 11.5 1.8 12.5 2.3
mA mA V V V mA V V V V
VIL VIH VPP IPP VOL VOH VID VLKO(1)
VCC = 2.7V 10% VCC = 2.7V 10% IOL = 1.8mA IOH = -100A
11.5
1. Sampled only, not 100% tested.
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M29W640FT, M29W640FB
Figure 8. Read Mode AC Waveforms
7 DC and AC parameters
tAVAV A0-A20/ A-1 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ7/ DQ8-DQ15 tBHQV BYTE tELBL/tELBH tBLQZ
AI05559
VALID tAXQX
tEHQX tEHQZ
tGHQX tGHQZ VALID
Figure 9.
Page Read AC Waveforms
A2-A21
VALID ADDRESS
A0-A1
VALID tAVQV
VALID
VALID
VALID
E tELQV tEHQX tEHQZ G tGHQX tGLQV DQ0-DQ15 VALID DATA tAVQV1 VALID DATA VALID DATA tGHQZ
VALID DATA
AI11553
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7 DC and AC parameters
M29W640FT, M29W640FB
Table 13.
Symbol
Read AC Characteristics
Alt Parameter Test Condition M29W640FT, M29W640FB 60 70 70 ns Unit
tAVAV tAVQV tAVQV1 tELQX(1) tELQV tGLQX(1) tGLQV tEHQZ(1) tGHQZ(1) tEHQX tGHQX tAXQX tELBL tELBH tBLQZ tBHQV
tRC tACC tPAGE tLZ tCE tOLZ tOE tHZ tDF
Address Valid to Next Address Valid
E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL
Min
60
Address Valid to Output Valid
Max
60
70
ns
Address Valid to Output Valid (Page) Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Chip Enable, Output Enable or Address Transition to Output Transition
Max Min Max Min Max Max Max
25 0 60 0 25 25 25
25 0 70 0 25 25 25
ns ns ns ns ns ns ns
tOH
Min
0
0
ns
tELFL tELFH tFLQZ tFHQV
Chip Enable to BYTE Low or High BYTE Low to Output Hi-Z BYTE High to Output Valid
Max Max Max
5 25 30
5 25 30
ns ns ns
1. Sampled only, not 100% tested.
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M29W640FT, M29W640FB
Figure 10. Write AC Waveforms, Write Enable Controlled
tAVAV A0-A20/ A-1 VALID tWLAX tAVWL E tELWL G tGHWL W tWLWH tWHGL tWHEH
7 DC and AC parameters
tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 VALID tWHDX
VCC tVCHEL RB tWHRL
AI05560
39/72
7 DC and AC parameters
M29W640FT, M29W640FB
Table 14.
Symbol
Write AC Characteristics, Write Enable Controlled
Alt Parameter M29W640FT, M29W640FB 60 70 70 0 45 45 0 0 30 0 45 0 0 30 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit
tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tWHGL tWHRL(1) tVCHEL
tWC tCS tWP tDS tDH tCH tWPH tAS tAH
Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low
Min Min Min Min Min Min Min Min Min Min Min Max Min
60 0 45 45 0 0 30 0 45 0 0 30 50
tOEH tBUSY tVCS
Write Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Chip Enable Low
1. Sampled only, not 100% tested.
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M29W640FT, M29W640FB
Figure 11. Write AC Waveforms, Chip Enable Controlled
tAVAV A0-A20/ A-1 VALID tELAX tAVEL W tWLEL G tGHEL E tELEH tEHGL tEHWH
7 DC and AC parameters
tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 VALID tEHDX
VCC tVCHWL RB tEHRL
AI05561
41/72
7 DC and AC parameters
M29W640FT, M29W640FB
Table 15.
Symbol tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tEHGL tEHRL(1) tVCHWL
Write AC Characteristics, Chip Enable Controlled
M29W640FT, M29W640FB Alt tWC tWS tCP tDS tDH tWH tCPH tAS tAH Parameter 60 Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low tOEH Chip Enable High to Output Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 60 0 45 45 0 0 30 0 45 0 0 30 50 70 70 0 45 45 0 0 30 0 45 0 0 30 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit
tBUSY Program/Erase Valid to RB Low tVCS VCC High to Write Enable Low
1. Sampled only, not 100% tested.
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M29W640FT, M29W640FB
Figure 12. Reset/Block Temporary Unprotect AC Waveforms
7 DC and AC parameters
W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX tPHPHH tPLYH
AI02931B
Figure 13. Accelerated Program Timing Waveforms
VPP VPP/WP VIL or VIH tVHVPP
tVHVPP
AI05563
Table 16.
Symbol tPHWL(1) tPHEL tPHGL
(1)
Reset/Block Temporary Unprotect AC Characteristics
Alt Parameter M29W640FT, M29W640FB Unit
tRH
RP High to Write Enable Low, Chip Enable Low, Output Enable Low
Min
50
ns
tRHWL(1) tRHEL(1) tRHGL
(1)
tRB
RB High to Write Enable Low, Chip Enable Low, Output Enable Low
Min
0
ns
tPLPX tPLYH tPHPHH(1) tVHVPP(1)
tRP tREADY tVIDR
RP Pulse Width RP Low to Read Mode RP Rise Time to VID VPP Rise and Fall Time
Min Max Min Min
500 50 500 250
ns s ns ns
1. Sampled only, not 100% tested.
43/72
8 Package mechanical
M29W640FT, M29W640FB
8
Package mechanical
Figure 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
1
48
e
D1
B
24
25
L1 A2 A
E1 E
DIE
A1 C CP
L
TSOP-G
1. Drawing is not to scale.
Table 17.
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters inches Max 1.200 0.100 1.000 0.220 0.050 0.950 0.170 0.100 0.150 1.050 0.270 0.210 0.100 12.000 20.000 18.400 0.500 0.600 0.800 3 0 5 11.900 19.800 18.300 - 0.500 12.100 20.200 18.500 - 0.700 0.4724 0.7874 0.7244 0.0197 0.0236 0.0315 3 0 5 0.4685 0.7795 0.7205 - 0.0197 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0039 0.4764 0.7953 0.7283 - 0.0276
Symbol Typ A A1 A2 B C CP D1 E E1 e L L1 a Min
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M29W640FT, M29W640FB
8 Package mechanical
Figure 15. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, Package Outline
D FD FE SD D1
SE E E1 BALL "A1" ddd
e e A A1 b A2
BGA-Z32
1. Drawing is not to scale.
Table 18.
Symbol
TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data
millimeters Typ Min Max 1.200 0.260 0.900 0.350 6.000 4.000 5.900 - 0.450 6.100 - 0.100 8.000 5.600 0.800 1.000 1.200 0.400 0.400 7.900 - - - - - - 8.100 - - - - - - 0.3150 0.2205 0.0315 0.0394 0.0472 0.0157 0.0157 0.3110 - - - - - - 0.2362 0.1575 0.0138 0.2323 - 0.0102 0.0354 0.0177 0.2402 - 0.0039 0.3189 - - - - - - Typ inches Min Max 0.0472
A A1 A2 b D D1 ddd E E1 e FD FE SD SE
45/72
9 Part Numbering
M29W640FT, M29W640FB
9
Table 19.
Example:
Part Numbering
Ordering Information Scheme
M29W640FB 70 N 6 F
Device Type M29 Operating Voltage W = VCC = 2.7 to 3.6V Device Function 640F = 64 Mbit (x8/x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 60 = 60ns 70 = 70ns Package N = TSOP48: 12 x 20 mm ZA = TFBGA48: 6x8mm, 0.80 mm pitch Temperature Range 6 = 40 to 85 C Option E = ECOPACK Package, Standard Packing F = ECOPACK Package, Tape & Reel Packing
Note: This product is also available with the Extended Block factory locked. For further details and ordering information contact your nearest ST sales office.
Devices are shipped from the factory with the memory content bits erased to 1. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
46/72
M29W640FT, M29W640FB
9 Part Numbering
Appendix A Block addresses
Table 20.
Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Top Boot Block Addresses, M29W640FT
KBytes/ KWords 64/32 64/32 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 1A0000h-1AFFFFh 1B0000h-1BFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh Protection Group 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh Protection Group Protection Block Group (x8) 000000h-00FFFFh(1) 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh (x16) 000000h-007FFFh(1) 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh
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9 Part Numbering
M29W640FT, M29W640FB
Block 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
KBytes/ KWords 64/32 64/32
Protection Block Group
(x8) 1C0000h-1CFFFFh 1D0000h-1DFFFFh
(x16) 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh
Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 3A0000h-3AFFFFh 3B0000h-3BFFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh
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M29W640FT, M29W640FB
9 Part Numbering
Block 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91
KBytes/ KWords 64/32 64/32
Protection Block Group
(x8) 3C0000h-3CFFFFh 3D0000h-3DFFFFh
(x16) 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh
Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 5A0000h-5AFFFFh 5B0000h-5BFFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh
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Block 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
KBytes/ KWords 64/32 64/32
Protection Block Group
(x8) 5C0000h-5CFFFFh 5D0000h-5DFFFFh
(x16) 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh
Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 7A0000h-7AFFFFh 7B0000h-7BFFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh
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Block 124 125 126 127 128 129 130 131 132 133 134
KBytes/ KWords 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4
Protection Block Group
(x8) 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7F1FFFh 7F2000h-7F3FFFh
(x16) 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F8FFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh
Protection Group
7F4000h-7F5FFFh 7F6000h-7F7FFFh 7F8000h-7F9FFFh 7FA000h-7FBFFFh 7FC000h-7FDFFFh 7FE000h-7FFFFFh
1. Used as the Extended Block Addresses in Extended Block mode.
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Table 21.
Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Bottom Boot Block Addresses, M29W640FB
KBytes/ KWords 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 160000h-16FFFFh 170000h-17FFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh Protection Group Protection Block Group (x8) 000000h-001FFFh(1) 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh (x16) 000000h-000FFFh(1) 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh
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Block 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
KBytes/ KWords 64/32 64/32
Protection Block Group
(x8) 180000h-18FFFFh 190000h-19FFFFh
(x16) 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh
Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 360000h-36FFFFh 370000h-37FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh
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Block 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94
KBytes/ KWords 64/32 64/32
Protection Block Group
(x8) 380000h-38FFFFh 390000h-39FFFFh
(x16) 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh
Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 560000h-56FFFFh 570000h-57FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh
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Block 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
KBytes/ KWords 64/32 64/32
Protection Block Group
(x8) 580000h-58FFFFh 590000h-59FFFFh
(x16) 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh
Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 760000h-76FFFFh 770000h-77FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh
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Block 127 128 129 130 131 132 133 134
KBytes/ KWords 64/32 64/32
Protection Block Group
(x8) 780000h-78FFFFh 790000h-79FFFFh
(x16) 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh
Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 7E0000h-7EFFFFh 7F0000h-7FFFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh
1. Used as the Extended Block Addresses in Extended Block mode.
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Appendix B Common Flash Interface (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 22, 23, 24, 25, 26, and 27, show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 27: Security Code Area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Table 22. Query Structure Overview
Sub-section Name x16 10h 1Bh 27h 40h 61h x8 20h 36h 4Eh 80h C2h CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Security Code Area Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) 64 bit unique device number Description
Address
1. Query data are always presented on the lowest order data outputs.
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Table 23.
CFI Query Identification String
Data Description Value "Q" Query Unique ASCII String "QRY" "R" "Y" AMD Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Compatible Address for Primary Algorithm extended Query table (see Table 26) P = 40h
Address x16 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah x8 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h Address for Alternate Algorithm extended Query table 0000h NA Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported NA
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'.
Table 24.
CFI Query System Interface Information
Data Description VCC Logic Supply Minimum Program/Erase voltage Value
Address x16 x8
1Bh
36h
0027h
bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV VCC Logic Supply Maximum Program/Erase voltage
2.7V
1Ch
38h
0036h
bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV VPP [Programming] Supply Minimum Program/Erase voltage
3.6V
1Dh
3Ah
00B5h
bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV VPP [Programming] Supply Maximum Program/Erase voltage
11.5V
1Eh
3Ch
00C5h
bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV Typical timeout per single byte/word program = 2n s Typical timeout for minimum size write buffer program = 2n s Typical timeout per individual Block Erase = Typical timeout for full Chip Erase = 2n ms Maximum timeout for byte/word program = 2n times typical Maximum timeout for write buffer program = 2n times typical 2n ms
12.5V
1Fh 20h 21h 22h 23h 24h
3Eh 40h 42h 44h 46h 48h
0004h 0000h 000Ah 0000h 0004h 0000h
16s NA 1s NA 256 s NA
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Address Data x16 25h 26h x8 4Ah 4Ch 0003h 0000h Maximum timeout per individual Block Erase = 2n times typical Maximum timeout for Chip Erase = 2n times typical 8s NA Description Value
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Table 25.
Device Geometry Definition
Data Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions. It specifies the number of regions containing contiguous Erase Blocks of the same size. Region 1 Information Number of Erase Blocks of identical size = 0007h+1 Region 1 Information Block size in Region 1 = 0020h * 256 byte Region 2 Information Number of Erase Blocks of identical size= 007Eh+1 Region 2 Information Block size in Region 2 = 0100h * 256 byte Region 3 Information Number of Erase Blocks of identical size=007Fh+1 Region 3 Information Block size in Region 3 = 0000h * 256 byte Region 4 Information Number of Erase Blocks of Identical size=007Fh+1 Region 4 Information Block size in Region 4 = 0000h * 256 byte Value
Address x16 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch x8 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 0017h 0002h 0000h 0004h 0000h 0002h 0007h 0000h 0020h 0000h 007Eh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 8 MByte x8, x16 Async. 16 Bytes 2 8 8Kbyte 127 64Kbyte
0 0 0 0
1. For Bottom Boot devices, Erase Block Region 1 is located from address 000000h to 007FFFh and Erase Block Region 2 from address 008000h to 3FFFFFh. For Top Boot devices, Erase Block Region 1 is located from address 000000h to 3F7FFFh and Erase Block Region 2 from address 3F8000h to 3FFFFFh.
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Table 26. Primary Algorithm-Specific Extended Query Table
Data x16 40h 41h 42h 43h 44h 45h x8 80h 82h 84h 86h 88h 8Ah 0050h 0052h 0049h 0031h 0033h 0000h Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (bits 1 to 0) 00h = required, 01h = not required Silicon Revision Number (bits 7 to 2) Erase Suspend 00h = not supported, 01h = Read only, 02 = Read and Write Description
9 Part Numbering
Address Value "P" Primary Algorithm extended Query table unique ASCII string "PRI" "R" "I" "1" "3" Yes
46h 47h 48h 49h 4Ah 4Bh 4Ch
8Ch 8Eh 90h 92h 94h 96h 98h
0002h 0004h 0001h 0004h 0000h 0000h 0001h
2 4 Yes 04 No No Yes
Block Protection 00h = not supported, x = number of blocks per protection group Temporary Block Unprotect 00h = not supported, 01h = supported Block Protect /Unprotect 04 = M29W640F Simultaneous Operations, 00h = not supported Burst Mode: 00h = not supported, 01h = supported Page Mode: 00h = not supported, 01h = 4 page word, 02h = 8 page word VPP Supply Minimum Program/Erase voltage
4Dh
9Ah
00B5h
bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP Supply Maximum Program/Erase voltage
11.5V
4Eh
9Ch
00C5h
bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Top/Bottom Boot Block Flag 02h = Bottom Boot device 03h = Top Boot device Program Suspend 00h = Not Supported 01h = Supported
12.5V
4Fh
9Eh
0002h 0003h 0001h
-
50h
A0h
Supported
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Table 27.
Security Code Area
Data Description
Address x16 61h 62h 63h 64h x8 C3h, C2h C5h, C4h C7h, C6h C9h, C8h XXXX XXXX 64 bit: unique device number XXXX XXXX
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Appendix C Extended Memory Block
The M29W640F has an extra block, the Extended Block, that can be accessed using a dedicated command. This Extended Block is 128 Words in x16 mode and 256 Bytes in x8 mode. It is used as a security block to provide a permanent security identification number) or to store additional information. The Extended Block is either Factory Locked or Customer Lockable, its status is indicated by bit DQ7. This bit is permanently set to either `1' or `0' at the factory and cannot be changed. When set to `1', it indicates that the device is factory locked and the Extended Block is protected. When set to `0', it indicates that the device is customer lockable and the Extended Block is unprotected. Bit DQ7 being permanently locked to either `1' or `0' is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. Bit DQ7 is the most significant bit in the Extended Block Verify Code and a specific procedure must be followed to read it. See "Extended Memory Block Verify Code" in Table 3: Bus Operations, BYTE = VIL and Table 4: Bus Operations, BYTE = VIH, for details of how to read bit DQ7. The Extended Block can only be accessed when the device is in Extended Block mode. For details of how the Extended Block mode is entered and exited, refer to the Section 4.3.1: Enter Extended Block command and Section 4.3.2: Exit Extended Block command, and to Table 5 and Table 6: Commands, 8-bit mode, BYTE = VIL.
C.1
Factory Locked Extended Block
In devices where the Extended Block is factory locked, the Security Identification Number is written to the Extended Block address space (see Table 28: Extended Block Address and Data) in the factory. The DQ7 bit is set to `1' and the Extended Block cannot be unprotected.
C.2
Customer Lockable Extended Block
A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to `0' and the Extended Block unprotected. It is up to the customer to program and protect the Extended Block but care must be taken because the protection of the Extended Block is not reversible. There are two ways of protecting the Extended Block: Issue the Enter Extended Block command to place the device in Extended Block mode, then use the In-System Technique with RP either at VIH or at VID (refer to Appendix D, Section D.2: In-System Technique and to the corresponding flowcharts, Figure 18 and Figure 19, for a detailed explanation of the technique). Issue the Enter Extended Block command to place the device in Extended Block mode, then use the Programmer Technique (refer to Appendix D, Section D.1: Programmer Technique and to the corresponding flowcharts, Figure 16 and Figure 17, for a detailed explanation of the technique). Once the Extended Block is programmed and protected, the Exit Extended Block command must be issued to exit the Extended Block mode and return the device to Read mode.
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Table 28.
Extended Block Address and Data
Address x8 x16 000000h-00000Fh 000010h-00007Fh Factory Locked Security Identification Number Determined by Customer Unavailable Data Customer Lockable
000000h-00020Fh 000021h-0000FFh
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Appendix D Block Protection
Block protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to Appendix A: Block addresses, Table 20 and Table 21 for details of the Protection Groups. Once protected, Program and Erase operations within the protected group fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section.
D.1
Programmer Technique
The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a group of blocks follow the flowchart in Figure 16: Programmer Equipment Group Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. To unprotect the chip follow Figure 17: Programmer Equipment Chip Unprotect Flowchart. Table 29: Programmer Technique Bus Operations, BYTE = VIH or VIL, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
D.2
In-System Technique
The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP(1). This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. To protect a group of blocks follow the flowchart in Figure 18: In-System Equipment Group Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 19: In-System Equipment Chip Unprotect Flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
Note:
RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block.
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Table 29.
Programmer Technique Bus Operations, BYTE = VIH or VIL
E G W Address Inputs A0-A21 A9 = VID, A12-A21 = Block Address Others = X A9 = VID, A12 = VIH, A15 = VIH Others = X A0, A2, A3 = VIL, A1 = VIH, A6 = VIL, A9 = VID, A12-A21 = Block Address Others = X VIL VIL VIH A0, A2, A3 = VIL, A1 = VIH, A6 = VIH, A9 = VID, A12-A21 = Block Address Others = X Data Inputs/Outputs DQ15A-1, DQ14-DQ0 X
Operation Block (Group) Protect(1) Chip Unprotect
VIL VID
VID VID
VIL Pulse VIL Pulse
X Pass = XX01h Retry = XX00h
Block (Group) Protection Verify
VIL
VIL
VIH
Block (Group) Unprotection Verify
Retry = XX01h Pass = XX00h
1. Block Protection Groups are shown in Appendix A, Tables 20 and 21.
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Figure 16. Programmer Equipment Group Protect Flowchart
START
9 Part Numbering
ADDRESS = GROUP ADDRESS Set-up
W = VIH n=0
G, A9 = VID , E = VIL
Wait 4s Protect W = VIL Wait 100s
W = VIH
E, G = VIH, A0, A2, A3 = VIL, A1 =VIH, A6 =VIL, A9 = VID, Others = X
E = VIL Wait 4s
Verify
G = VIL Wait 60ns
Read DATA
DATA NO = 01h YES A9 = VIH E, G = VIH End PASS ++n = 25 YES A9 = VIH E, G = VIH FAIL
AI11555
NO
1. Block Protection Groups are shown in Appendix A, Tables 20 and 21.
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9 Part Numbering
M29W640FT, M29W640FB
Figure 17. Programmer Equipment Chip Unprotect Flowchart
START
PROTECT ALL GROUPS Set-up
n=0 CURRENT GROUP = 0
A6, A12, A15 = VIH (1) E, G, A9 = VID
Wait 4s Unprotect
W = VIL Wait 10ms
W = VIH E, G = VIH
ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3 = VIL, A1 =VIH, A6 =VIL, A9 = VID, Others = X
E = VIL Wait 4s
G = VIL Wait 60ns
INCREMENT CURRENT GROUP
Verify
Read DATA
NO
DATA = 00h
YES
NO
++n = 1000 YES
LAST GROUP YES A9 = VIH E, G = VIH PASS
NO
End
A9 = VIH E, G = VIH FAIL
AI11556
1. Block Protection Groups are shown in Appendix A, Tables 20 and 21.
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Figure 18. In-System Equipment Group Protect Flowchart
START Set-up
9 Part Numbering
n=0 RP = VID WRITE 60h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH
Protect
WRITE 60h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH
Wait 100s
WRITE 40h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH Verify
Wait 4s READ DATA ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH
DATA NO = 01h YES RP = VIH End ISSUE READ/RESET COMMAND ++n = 25 YES RP = VIH ISSUE READ/RESET COMMAND NO
PASS
FAIL
AI11563
2. Block Protection Groups are shown in Appendix A, Tables 20 and 21. 3. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block.
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9 Part Numbering
M29W640FT, M29W640FB
Figure 19. In-System Equipment Chip Unprotect Flowchart
START
PROTECT ALL GROUPS
n=0 CURRENT GROUP = 0
RP = VID WRITE 60h ANY ADDRESS WITH A0, A2, A3, A6 = VIL, A1 = VIH
WRITE 60h ANY ADDRESS WITH A0, A2, A3 = VIL, A1, A6 = VIH
Wait 10ms
WRITE 40h ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3 = VIL, A1, A6 = VIH
Wait 4s INCREMENT CURRENT GROUP
READ DATA ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3 = VIL, A1, A6 = VIH
NO
DATA = 00h
YES
NO
++n = 1000 YES RP = VIH
LAST GROUP YES RP = VIH
NO
ISSUE READ/RESET COMMAND
ISSUE READ/RESET COMMAND
FAIL
PASS
AI11564
1. Block Protection Groups are shown in Appendix A, Tables 20 and 21.
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10 Revision History
10
Table 30.
Date
Revision History
Document Revision History
Version 0.1 0.2 First Issue. Asynchronous Page mode added. 70ns speed class added. Device codes modified. TFBGA63 replaced by TFBGA48 6x8 package. ECOPACK text updated Page size changed to 4 Word. 90ns speed class removed. Quadruple Word/Octuple Byte Program command added. Table 3: Bus Operations, BYTE = VIL and Table 4: Bus Operations, BYTE = VIH: A0A21 addresses for reading the Device Code, the Manufacturer Code, the Extended Memory Block Verify Code, and the Block Protection Status, have been updated. Appendix D: Block Protection: Table 29: Programmer Technique Bus Operations, BYTE = VIH or VIL: A0-A21 addresses updated for Block Protection/Unprotection Verify using the Programmer technique. Datasheet status changed to "Full Datasheet". 60ns speed class added. Program Suspend and Resume added. Section 2.8: VPP/Write Protect (VPP/WP) and Section 4.2: Fast Program commands. Section 4: Command Interface restructured. Table 28: Extended Block Address and Data updated. Double Byte Program commands added in Section 4: Command Interface. Table 3: Bus Operations, BYTE = VIL and Table 4: Bus Operations, BYTE = VIH.: A6 changed from VIH to VIL for Read Block Protection Status operation. Revision Details
01-Mar-2005 17-May-2005
07-Oct-2005
1.0
02-Dec-2005
2
15-Dec-2005
3
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